-- Generator adresu
-- Wejscia: INPUT0[7..0] .. INPUT7[7..0]
-- Wyjscie: OUTPUT[3..0]
-- Wejscia sterujace:
-- S[2..0]

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

entity GA is
  generic (delay : time := 5 ns);
  port (INPUT0, INPUT1, INPUT2, INPUT3, INPUT4, INPUT5, INPUT6, INPUT7  : in std_logic_vector(7 downto 0);
        OUTPUT : out std_logic_vector(3 downto 0);
        S      : in std_logic_vector(2 downto 0));
end entity GA;

architecture GA_arch of GA is
begin
  process(S, INPUT0, INPUT1, INPUT2, INPUT3, INPUT4, INPUT5, INPUT6, INPUT7)
  begin
      case S is
        when "000" => OUTPUT <= INPUT0(3 downto 0) after delay;
        when "001" => OUTPUT <= INPUT1(3 downto 0) after delay;
        when "010" => OUTPUT <= INPUT2(3 downto 0) after delay;
        when "011" => OUTPUT <= INPUT3(3 downto 0) after delay;
        when "100" => OUTPUT <= INPUT4(3 downto 0) after delay;
        when "101" => OUTPUT <= INPUT5(3 downto 0) after delay;
        when "110" => OUTPUT <= INPUT6(3 downto 0) after delay;
        when "111" => OUTPUT <= INPUT7(3 downto 0) after delay;
        when others => OUTPUT <= "ZZZZ";
      end case;

  end process;
end architecture GA_arch;
